Could AMD’s Upcoming EPYC ‘Rome’ Server Processors Feature Up To 162 PCIe Lanes?

jwhyche (Slashdot reader #6,192) tipped us off to some interesting speculation about AMD’s upcoming Zen 2-based EPYC Rome server processors. “The new Epyc processor would be Gen 4 PCIe where Intel is still using Gen 3. Gen 4 PCIe features twice the bandwidth of the older Gen 3 specification.”

And now Tom’s Hardware reports:
While AMD has said that a single EPYC Rome processor could deliver up to 128 PCIe lanes, the company hasn’t stated how many lanes two processors could deliver in a dual-socket server. According to, there’s a distinct possibility EPYC could feature up to 162 PCIe 4.0 lanes in a dual-socket configuration, which is 82 more lanes than Intel’s dual-socket Cascade Lake Xeon servers. That even beats Intel’s latest 56-core 112-thread Platinum 9200-series processors, which expose 80 PCIe lanes per dual-socket server.

Patrick Kennedy at ServeTheHome, a publication focused on high-performance computing, and RetiredEngineer on Twitter have both concluded that two Rome CPUs could support 160 PCIe 4.0 lanes. Kennedy even expects there will be an additional PCIe lane per CPU (meaning 129 in a single socket), bringing the total number of lanes in a dual-socket server up to 162, but with the caveat that this additional lane per socket could only be used for the baseboard management controller (or BMC), a vital component of server motherboards… If @RetiredEngineer and ServeTheHome did their math correctly, then Intel has even more serious competition than AMD has let on.

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